Cryogenic circuit fabrication



May 21, 1968 I J. w. BREMER CRYOGENIC CIRCUIT FABRICATION Original FiledMarch 14, 1962 5 Sheets-Sheet l s o 0000000 0 wwoooo 000 0 l0987654INVENTOR JOHN W. BREMER ATTORNEY May 21, 1968 .1. w. BREMER 3,333,753

CRYOGENIC CIRCUIT FABRI CATION Original Filed March 14. 1962 5Sheets-Sheet 2 INVENTOR.

JOHN w. BREMER ATTORNEY y 1, 1968 J. w. BREMER 3,383,758

CRYOGENIC CIRCUIT FABRICATION.

Original Filed March 14. 1962 5 Sheets-Sheet 3 INVENTOR.

JOHN W. BREMER JMw/z ATTORNEY y 21, 1968 J. w. BREMER 3,383,758

CRYOGENIC CIRCUIT FABRICATION Original Filed March 14. 1962 5Sheets-Sheet 4 I NVENTOR.

JOHN W. BREMER JMM/Z, Z/WM ATTORNEY May 21, 1968 J. w. BREMER 3,383,758

CRYOGENIC CIRCUIT FABRICATION Original Filed March 14, 1962 5Sheets-Sheet 5 EVAPORATE TIN THROUGH A MASK ON INSULATING SUB- STRATE TOFORM PATTERN OF GATE CONDUCTORS I2(II" I2(n)- EVAPORATE SILICON MONOXIDETHROUGH PATTERN DE- FINING MASK OVER GATE CONDUCTOR LAYER TO FORMINSULATING FILM I6.

EVAPORATE FILM OF LEAD OVER FOREGOING MATERIALS.

COVER LEAD FILM WITH LAYER OF PHOTORESIST MATER- IAL.

EXPOSE PHOTORESIST LAYER TO LIGHT THROUGH A NEGA" TIVE OF THE PATTERN OFCONTROL AND INTERCONNECT- ING CONDUCTORS.

APPLY PHOTODEVELOPER TO WASH AWAY UNEXPOSED POR- TIONS OF PHOTORESISTLAYER.

APPLY AN ETCHING SOLUTION TO REMOVE UNPROTECTED PORTIONS OF LEAD FILMTHUS FORMING CONTROL CON- DUCTORS l7(|)-I7In) AND INTERCONNECTINGCONDUCTORS I3 AND I8.

INVENTOR.

JOHN W. BREMER Dime g ATTORNEY Jig..9

United States Patent 3,383,758 CRYOGENIC CIRCUIT FABRICATIUN John W.Bremer, Phoenix, Ariz., assignor to General This application is acontinuation of application Ser. No. 179,596, filed Mar. 14, 1962, nowabandoned.

This invention relates to cryogenic devices and particularly to thefabrication of complex and high density cryogenic circuitconfigurations.

Certain electrical conductors are known to exhibit a loss of electricalresistance at supercold temperatures approaching absolute zero and toregain resistance in the presence of a certain critical magnetic field.The critical field depends upon the particular superconductive materialas well as its temperature. Superconductive materials requiringcomparatively high critical magnetic fields are known as hardsuperconductors while those requiring comparatively low criticalmagnetic fields are known as soft superconductors.

Superconductors can be used to form a cryotron or superconductiveswitch. In the preferred thin-film form the cryotron comprises a gateconductor film in the order of 0.3-1.0 micron thickness of softsuperconductive material which is crossed by a narrow control conductorfilm also in the order of 0.3-1.0 micron thickness insulated V therefromand preferably formed of hard superconductive material. Both the gateconductor and the control conductor are thus normally in thesuperconducting state. If sufiicient current is caused to flow throughthe control conductor the resulting magnetic field causes the gateconductor to become resistive in the region of the crossover.

Large numbers of such cryogenic devices may be interconnected to formlarge capacity switching and computing circuit assemblies as exemplifiedin a US. Patent No. 3,004,705 entitled Superconductive Computer andComponents Therefor, issued to John W. Bremer on Oct. 17, 1961 andassigned to the same assignee as the present invention.

Because of low heat losses, cryogenic devices of the thin-film form maybe greatly miniaturized and formed on a small area. For example, it isdesirable to form at least 350 cryotrons with interconnecting conductorson a single substrate.

Cryogenic assemblies have typically been formed by a masking techniquewherein the soft superconductive gate forming material is deposited on asuitable substrate through a pattern defining mask. A pattern ofinsulating material is next deposited through a second pattern definingmask. The hard superconductive control forming material is thendeposited through a third pattern defining mask.

In a complex circuit many interconnecting conductors are usuallyrequired. Some of these interconnecting conductors may usually be formedin the gate and control conductor layers. However, due to masklimitations, several additional layers of conducting material, suitablyinsulated from the underlying materials, will usually be required toprovide the requisite control conductors.

The layer containing the control conductors is usually the most complexand dense especially when it is attempted to include therein as many ofthe interconnecting conductors as possible to thereby reduce the numberof additional layers required for interconnecting conductors. In such acase the pattern defining mask becomes flimsy and fragile, making itdifficult and expensive if not impossible to fabricate and use.Furthermore, the design 3,383,758 Patented May 21, 1968 of the mask mustordinarily be such that both ends of narrow strips of the mask aresupported. Also, the narrow strips of a mask must ordinarily be straightwhereas from a design standpoint it is often desirable for a conductorto change direction at one or more points. These factors are a severeconstraint on the layout of the patterns with the usual result thatadditional layers are required for interconnecting conductors.

In a large cryogenic system it is desirable to form as much of thecryogenic circuitry as possible on a single substrate in order to avoidthe diificulties of making interconnections between substrates such asunreliable connections, undesirable inductance, poor utilization ofspace and the like.

Thus it is desirable to form cryogenic circuit assemblies on relativelylarge substrates, on the order of 3 by 4 inches or larger. It isdifficult to construct the necessary large masks for accurate depositionof conductor patterns so that characteristics are uniform because largecomplex masks tend to warp and thereby cause variable shadowing, thatis, irregular conductor edges. Thus with the masking technique it hasbeen impractical to form dense conductor patterns with masks havingdimensions greater than about two inches.

This problem may be overcome to some degree by using many small masksand depositing only a small area of a pattern at a time. However, thisprocess increases the time and cost of fabrication and introduces theproblem of registration of the separately deposited portions.

It is therefore an object of the invention to provide improved cryotronand cryogenic circuit assemblies.

It is a more specific object of the invention to fabricate dense andcomplex cryogenic circuit assemblies.

Another specific object of the invention is to provide a complexthin-film cryogenic circuit assembly having first and second conductinglayers wherein the first layer includes a pattern of gate conductors andthe second layer includes a pattern of control conductors and whereinall interconnecting conductors are included in the first and secondlayers whereby additional conducting layers for interconnectingconductors are not required.

Another object of the invention is to form large amounts of cryogeniccircuitry on a single substrate.

Another object of the invention is to form complex cryogenic circuits onrelatively large substrates having dimensions on the order of fourinches and greater.

It is a further object of the invention to more accurately fabricatecryogenic circuit assemblies of predetermined characteristics.

These and other objects of the invention are achieved by employing aphotoetching process to form, at least,

the pattern of control and interconnecting conductors of the controlconductor layer as is more fully explained in the following detaileddescription of the present invention with reference to the accompanyingdrawings in which:

FIGURE 1 is a perspective view illustrating an example of a thin-filmcryotron circuit assembly;

FIGURE 2 is a graph of critical magnetic field versus temperature forvarious superconductors;

FIGURE 3 is a general illustration of evaporation apparatus;

FIGURE 4 is an illustration of a mask for depositing the gate conductorsof the assembly of FIG. 1;

FIGURE 5 is an illustration of a mask for depositing the layer ofinsulating material of the assembly of FIG. 1;

FIGURE 6 is an illustration of an impractical mask which would berequired to deposit the control conductor layer in a single step;

FIGURE 7 is an illustration of a mask for depositing part of the controlconductor layer;

FIGURE 8 is an illustration of a mask for depositing an interconnectingconductor in an additional layer; and

FIGURE 9 is a diagram of the steps of the process of fabricating thecryotron circuit assembly of FIG. 1 according to the present invention.

Shown in FIG. 1 is a superconductive switching matrix as an example of acryotron circuit assembly for the purpose of explaining the fabricatingmethod of the present invention.

While the illustrated switch is a relatively simple cryogenic circuit itwill serve to illustrate how the fabrication method of the presentinvention may be applied to more complex circuits such as a thin-filmform of the circuits shown in the above-mentioned Patent No. 3,004,705

FIG. 2 illustrates the relative critical magnetic fields (Hc) forexemplary superconductive materials with the field strength required toreturn the material to its resistive state plotted against operatingtemperature. Cryotron circuits may be conveniently operated at atemperature of around 3.6 degrees Kelvin (K.). In such case theexemplary materials tin (Sn) and tantalum (Ta) are soft superconductivematerials, that is, a relatively low magnetic field causes them tobecome resistive, and lead (Pb) and niobium (Nb) are hardsuperconductive materials.

The switching matrix of FIG. 1 is shown and described in a copending US.patent application Ser. No. 78,118, entitled, Cryogenic Circuitry, filedby Vernon L. New- 101186 and John W. Bremer on Dec. 23, 1960, andassigned to the same assignee as the present invention.

The construction and operation of the switching matrix is briefly asfollows. A substrate for supporting the cryotron circuitry comprises asuitable base 10 having an insulating film or surface 11. (In someapplications it is desirable to provide a shield plane beneath thecryogenic circuit. In such a case the base or substrate 10 may be formedof superconductive material. Alternatively, the substrate 10 may beformed of a material such as glass and a thin film of superconductivematerial may be provided between the substrate and the insulating film11.)

Formed on the insulating surface 11 is a plurality of thin strips ofsoft superconductive material such as tin which form a plurality of gateconductors 12(1)12(n). A film of insulating material 16 is formed overthe gate conductors and over the substrate except for a strip 15 whichis left uncovered to expose the ends of the gate conductors.

Formed over the insulating film 16 is a plurality of strips of hardsuperconductive material such as lead which form a plurality of controlconductors 17(1)-17(n). The control conductors are connected together atone end by a strip 18. A strip 13, which is preferably continuous withstrip 18, makes electrical contact with the ends of the gate conductors12(1)12(n) and with a common lead 14.

When a current of sufficient magnitude is caused to flow in a selectedcontrol conductor, the resulting magnetic field causes the gateconductors to become resistive except for the one gate conductor beneaththe wide segment of the control conductor as is explained in theabovementioned application Ser. No. 78,118. For examples, if controlconductor 17(1) is selected all of the gate conductors become resistiveexcept gate conductors 12(n).

As mentioned hereinbefore the gate conductors of a cryogenic circuitassembly are generally wider than the control conductors and the gateconductor pattern is generally less dense than the control conductorpattern. For example, a gate conductor may have a width in the order of0.04 inch whereas the control conductor pattern may have controlconductors of about 0.002. inch in width and conductor spacing of 0.010inch. Therefore, in the detailed embodiment of the present inventiononly the control conductor pattern is formed by the photoetchingprocess, the gate conductor and insulating layers being formed by theconventional masking technique. It is specifically pointed out howeverthat where considerations such as the width of gate conductors anddensity of the gate conductor pattern make it desirable, the gateconductor pattern also may be formed by a photoetching process in amanner similar to that set forth hereinafter for forming the controlconductor pattern.

In order to illustrate some of the difficulties with the prior artmasking technique the use of this technique in the process offabricating the matrix switch of FIG. 1 will first be described afterwhich the fabrication of the matrix switch according to the presentinvention will he described to show how these difiiculties are overcomethereby.

To form the pattern of gate conductors 12(1)-12(n) on the insulatedsurface 11 of the base or substrate 10, the substrate 10 is placed in aconventional film evaporating apparatus indicated generally as 30 inFIG. 3. Shown in FIG. 4 is a mask 40 having a series of elongatedcutouts 41(1)41(n) corresponding to the gate conductors 12(1)12(n). Themask 40 is placed next to the base 10 as indicated by 3 1, FIG. 3. Theatmosphere of the evapcrating apparatus is evacuated (by means notshown) and superconducting material such as tin is evaporated from aboat 32 whereby a film of the material is deposited on the substrate inthe pattern defined by the mask.

The insulating layer 16 is next formed by evaporating a film of suitableinsulating material such as silicon monoxide through a pattern definingmask, such as a mask 50 shown in FIG. 5, over the gate conductor layer.In the present example the pattern defining mask is formed to preventdeposition of the insulating material in the area 15 to thus leave theends of the gate conductors exposed.

The control conductor layer comprising the control conductors 17(1)17(n) and interconnecting conductors 13 and 18 is next to be formed.Referring to FIG. 6 it is seen that in order to form this controlconductor layer pattern by the prior art masking technique in a singlelayer, a mask illustrated as a mask 60 is required. However, such a maskis generally impractical because of the unsupported ends of a series ofmask strips 61 (1)61(n). It will be appreciated that it is difficult toconstruct such a mask which will remain flat because strips which aresupported at only one end tend to twist or curl. This is particularlytrue when the strip width W is relatively small and the strip length Lis relatively large. For example, as mentioned hereinbefore, in a densecryogenic circuit pattern it is desirable to form conductors having alength L in the order of four inches or more and with spacing W betweenconductors in the order of 0.010 inch. It is thus generally impracticalto form a mask having the shortcomings of mask 60.

Therefore to form the control conductor layer pattern by the maskingtechnique additional conducting layers are usually required to containat least some of the interconnecting conductors. For example, thecontrol conductors 17 (1)-17 (n) and the interconnecting conductor 13may first be deposited by the use of a mask such as a mask 70illustrated in FIG. 7 which has formed therein a series of cutouts17(1)-71(n) corresponding to the control conductors 17(1)-17(n) and acutout 73 corresponding to interconnecting conductor 13.

The interconnecting conductor 18 is then deposited in an additionallayer to make electrical contact with the left ends of controlconductors 17(1)-17(n) and interconnecting conductor 13 by the use of amask such as a mask 80, illustrated in FIG. 8, which has a cutout 81corresponding to the interconnecting conductor 18.

Thus, even for the relatively simple cryogenic circuit illustrated inFIG. 1 an additional conducting layer is needed to form theinterconnecting conductors When the circuit is fabricated by the maskingtechnique. In fact for complex circuits as many as sixteen additionalconducting layers have been needed for interconnecting conductors.

In addition to the time and expense of depositing these additionallayers the difiiculty of depositing each layer so that it is in properregistration with the underlying layers is readily apparent.

Also, even with masks such as mask 70 shown in FIG. 7 wherein both endsof the strips are supported, it is difiicult to accurately depositclosely spaced narrow conductors because the strips tend to twist andwarp and cause variable shadowing, that is, the mask does not makeuniform contact so that the evaporated material is deposited irregularlyalong the edges of the mask strips. This difficulty will be furtherappreciated by considering that mask strips would have to be four incheslong or more and a few hundredths of an inch wide to achieve the desiredcircuit density on large substrates.

The foregoing difficulties among others of the prior art maskingtechnique may be overcome and dense cryogenic circuits may be formedwith great accuracy on relatively large as well as small substrates byusing the photoetching process of the present invention to form at leastthe control conductor layer as shown in FIG. 9 which sets forth thesteps of fabricating the cryogenic circuit of FIG. 1 according to thepresent invention. Also, all of the required interconnecting conductorsmay be formed in the gate and control conductor layers thus eliminatingthe difiiculties of depositing multiple interconnecting conductorlayers.

As mentioned hereinbefore, where the complexity or other factors make itdesirable the gate conductor layer may be formed by a photoetchingprocess similar to the process described hereinafter for the controlconductor layer. However, for the purpose of illustrating the presentinvention it is assumed that the gate conductor layer is deposited byevaporation through a suitable mask, such as the mask 40 of FIG. 4 fordepositing the gate conductors 12(1)12(n) of the present example, asdescribed hereinbefore.

Thus, assuming that the gate conductors 12(1)-12(n) have been formed onthe insulating film or surface 11, FIG. 1, and that the insulating layer16 has been formed over the gate conductor pattern by evaporation of theinsulating material through the mask 50, FIG. 5, as describedhereinbefore, the formation of the control conductor layer pattern,comprising control conductors 17(1)-17(n) and the interconnectingconductors 13 and 18, in accordance with the principles of the presentinvention will now be described by way of example.

The control conductor layer pattern is formed according to the presentinvention by first depositing, for example by evaporation, a film ofsuperconductive material such as lead over the entire exposed surface ofthe gate conductor and insulating layers. The pattern of control andinterconnecting conductors in then formed by the photoetching processsubstantially as follows:

The lead film is covered with a layer of photoresist material such asKodak KPR photoresist which may conveniently be applied by spraying ordipping.

The layer of photoresist material is dried, for example by spinning theassembly in appropriate spinning apparatus (not shown) and/ or by bakingin an oven.

The photoresist layer is then exposed to light through a negative of thedesired pattern of control and interconnecting conductors. To achieveaccuracy of dimensions of the pattern, the negative is preferablyproduced by first producing a greatly enlarged art master copy of thecontrol conductor layer pattern. The art master is then photographed andthe negative of the pattern is produced by photographic reductionpreferably in the order of to 1 or more.

The portions of the photoresist layer which are exposed to light becomerelatively insoluble thus forming a protective image pattern. For thesuggested photoresist material the light source may be, for example, a9'0 ampere arc lamp lighted for about one .minute at a distance of about30 inches.

A solution such as Kodak Photoresist Developer No. 1156 is next appliedby immersing the assembly in the solution for a period of about sixminutes after which the assembly is rinsed in distilled Water or freshdeveloper. These latter two steps result in a washing away of theunex'posed photoresist material whereby the desired pattern of the leadfilm is protected and the undesired portions are now exposed.

The exposed portion of the lead film is now etched away leaving thepattern of control and interconnecting conductors as protected by thephotoresist material.

A suitable etching solution is an aqueous ammonium molybdate solution ata temperature of about 20 degrees centigrade comprising 96.5 ml. of asaturated ammonium molybdate compound, (NH )6Mo O -4H O, to which isadded 50 ml. of concentrated nitric acid (70 perecnt HNO and 640 ml. ofdistilled water.

The etching solution is applied to remove the unprotected portions ofthe lead film, for example, by immersing the assembly in the etchingsolution, for a period of 1522 seconds.

Immediately following the etching period the assembly is washed indistilled Water or sodium hydroxide for about 22 seconds to remove anyadhering etching solution.

Immediately following this washing any adhering water is removed, forexample, by immersing the assembly in ethanol, to prevent undesirableoxidation of the edges of the lead strips which have been formed.

The photo-sensitized protective resist material may now be removed byimmersing the assembly in a resist remover solution such as KodakThinner No. 1121 for a period of about 10 seconds after which theassembly is again washed in ethanol.

The now completed control and interconnecting conductor pattern may beprotected from damage due to handling or the like by applying aprotective coating of a film-forming organic polymer such asmethylmethacrylate thereto.

As explained hereinbefore a cryotron switch is formed by a controlconductor crossing a gate conductor. Also, the aforementionedapplication No. 78,118 discloses how inactive crossovers can be formed.The number of crossovers per unit area, active and inactive, is onemeasure of the density of a cyrogenic circuit. Cryogenic circuits havingat least 700 crossovers, at least one-half of which are active, andhaving all the interconnecting conductors in the gate and controlconductor layers with interconnecting conductors of about 0.010 inch inwidth spaced by a like distance and with control conductors having awidth of about 0.002 inch within plus or minus ten percent have beenfabricate-d according to the present invention on a substrate area oftwelve square inches.

This density and accuracy would be difiicult and expensive if notimpossible to achieve with the prior art masking technique of formingthe conrtol conductor pattern.

Furthermore, the design of cryogenic circuit assemblies fabricatedaccording to the present invention may be easily and accurately changedby modifying the enlarged art master. This is in contrast to thedifiiculty and expense of producing a different mask as required fordesign changes when the prior art masking technique is employed.

Also, complicated and extensive cryogenic circuit assemblies may beaccurately fabricated according to the present invention on largesubstrates, having dimensions of four inches and more, whereas largemasks of complex patterns result in impractically long and narrow maskstrips and undue constraint on circuit pattern design.

While the principles of the invention have been made clear in theillustrative embodiments, there will be obvious to those skilled in theart, many modifications in structure, arrangement, proportions, theelements, materials, and components, used in the practice of theinvention, and otherwise, which are adapted for specific environmentsand operating requirements, without departing from these principles. Theappended claims are therefore intended to cover and embrace any suchmodifications within the limits only of the true spirit and scope of theinvention.

What is claimed is:

1. A method of fabricating a thin-film superconductive circuit on aninsulating substrate comprising the steps of: placing said substrate ina high-vacuum atmosphere; evaporating on said substrate through apattern defining mask a first pattern of superconductive material;forming a film of insulating material over selected portions of saidfirst pattern; evaporating a film of superconductive material having athickness of less than 10 microns over said foregoing materials;removing said substrate from said atmosphere; selectively removingportions of said film of superconductive material to form a secondpattern or" superconductive material; and placing said circuit in anenvironment wherein said superconductive material is normally in thesuperconductive state.

2. A method of fabricating a thin-film superconductive circuit assemblyon a substrate comprising the steps of: placing said substrate in ahigh-vacuum atmosphere; forming on said substrate a pattern of firstsuperconductive material; covering selected portions of said firstsuperconductive material with a film of insulating material; forming afilm of second superconductive material having a thickness of less than10 microns over said foregoing materials; removing said substrate fromsaid high-vacuum atmosphere; forming a pattern of etchant resistmaterial on said second superconductive material to protect selectedportions thereof; applying an etc-hing solution to said assembly to etchaway the unprotected portions of said second superconductive material;and placing said assembly in an atmosphere wherein said circuit isnormally superconductive.

3. A method of fabricating a thin-film superconductive circuit assemblyon a substrate comprising the steps of: forming on said substrate apattern of first superconductive material; covering selected portions ofsaid first superconductive material with a film of insulating material;forming a film of second superconductive material having a thickness ofless than 10 microns over said foregoing materials; coating said secondsuperconductive material with a photosensitive etchant resist material;exposing selected portions of said resist material tolight therebyforming a protective pattern thereof on said second superconductivematerial; removing the unexposed portions of said resist material;applying an etching solution to etch away the unprotected portions ofsaid second superconductive material; and placing said fabricatedassembly in an environment wherein said superconductive material isnormally in the superconductive state.

4. A method of fabricating a thin-film superconductive circuit assemblyon a substrate comprising the steps of:

depositing on said substrate through a pattern defining mask a patternof first superconductive material; covering selected portions of saidfirst superconductive material with a film of insulating material;form-ing a film of second superconductive material having a thickness ofless than 10 microns over said foregoing materials; coating said secondsuperconductive material with photosensitive etchant resist material;exposing selected portions of said resist material to light therebyforming a protective pattern thereof on said second superconductivematerial; removing the unexposed portions of said resist material;applying an etching solution to etch away the unprotected portions ofsaid second superconductive material; and placing said assembly in anenvironment wherein said superconductive material is normally in thesuperconductive state.

References Cited UNITED STATES PATENTS 2,777,192 1/1957 Albright et 211.3,058,852 10/1962 Cabwell et 211. 3,059,196 10/1962 Lentz. 3,075,866l/1963 Baker et a1. 3,091,556 5/ 1963 Behrndt et al. 3,100,267 8/1963CrOWe.

OTHER REFERENCES An Approach to Microminiature Printed Systems, by Buckand Shoulders, Proceedings of Eastern Joint Computer, 1958, pp. 55-59.

CHARLIE T. MOON, Primary Examiner.

P. M. COHEN, Assistant Examiner.

1. A METHOD OF FABRICATING A THIN-FILM SUPERCONDUCTIVE CIRCUIT ON ANINSULATING SUBSTRATE COMPRISING THE STEPS OF: PLACING SAID SUBSTRATE INA HIGH-VACUUM ATMOSPHERE; EVAPORATING ON SAID SUBSTRATE THROUGH APATTERN DEFINING MASK A FIRST PATTERN OF SUPERCONDUCTIVE MATERIAL;FORMING A FILM OF INSULATING MATERIAL OVER SELECTED PORTIONS OF SAIDFIRST PATTERN; EVAPORATING A FILM OF SUPERCONDUCTIVE MATERIAL HAVING ATHICKNESS OF LESS THAN 10 MICRONS OVER SAID FOREGOING MATERIALS;REMOVING SAID SUBSTRATE FROM SAID ATMOSPHERE; SELECTIVELY REMOVINGPORTIONS OF SAID FILM OF SUPERCONDUCTIVE MATERIAL TO FORM A SECONDPATTERN OF SUPERCONDUCTIVE MATERIAL; AND PLACING SAID CIRCUIT IN ANENVIRONMENT WHEREIN SAID SUPERCONDUCTIVE MATERIAL IS NORMALLY IN THESUPERCONDUCTIVE STATE.